Browse Prior Art Database

Simple Compatible System ROM Area Expansion

IP.com Disclosure Number: IPCOM000100585D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Smith, BA: AUTHOR

Abstract

This article describes a technique to use paged ROM to simulate overlays instead of using a hardfile to retrieve overlays.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Simple Compatible System ROM Area Expansion

       This article describes a technique to use paged ROM to
simulate overlays instead of using a hardfile to retrieve overlays.

      As the personal computer (PC) systems complexity has expanded
over the last few years, the on-board support software, POST and
BIOS, have grown in size to the point that not all of the required
code can be contained within the 128 KB memory space alloted for the
purpose by the architecture.  As a result some means of expanding the
available space is required.

      Fig. 1 shows in block diagram a design utilizing the method
disclosed herein.  The solution is to increase the total size of the
ROM module to 512 KB, and operate the chip in a paging mode.  This
allows for all of the BIOS to be contained on one chip, and the
desired portions are paged in during the power-on self-test (POST)
process and copied to dynamic RAM (DRAM) for later use.  Once POST
has completed, the ROM is disabled and a customized basic input
output system (BIOS) area in DRAM will be activated.  Paging is
accomplished by connecting the two high-order address bits to a
register in the processor's address space, below hex '100'.  At
power-on time the register will be set to a pre-determined value to
access the initial page of code, most likely POST.  When needed, the
microcode can program the register to any of the other three values
to access the additional pages contained within the chip, as
illustrated...