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Deposition Induced Self-Alignment Process

IP.com Disclosure Number: IPCOM000100591D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 72K

Publishing Venue

IBM

Related People

King, W: AUTHOR [+2]

Abstract

A process is shown in which a raised structure, e.g., a polysilicon gate, can be isolated in a self-aligned fashion from other components of a device.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Deposition Induced Self-Alignment Process

       A process is shown in which a raised structure, e.g., a
polysilicon gate, can be isolated in a self-aligned fashion from
other components of a device.

      Depending on the underlying topography, certain films, e.g.,
oxides, deposited in a Watkins-Johnson atmospheric chemical vapor
deposition (CVD) tool will exhibit a non-uniform thickness, as shown
in Fig. 1. Variations in deposited thickness (a/b ratios of 1.4/1.0
are commonly observed) is a function of the deposition parameters and
film composition. This effect is viewed as an annoying deposition
quirk; however, it may also be exploited for useful purposes. By
controlling the deposition parameters of the tool, the a/b ratio can
be made large enough so that an isotropic reactive ion etch (RIE) of
the oxide/film will result in a thick oxide on top of the polysilicon
when all oxide is removed over the diffusion region, as shown in Fig.
2. This basic concept can be utilized to provide a wide range of VLSI
fabrication needs.

      Fig. 3 shows a typical M1 diffusion contact layout compared
with a borderless to polysilicon contact process. Fig. 4 shows a
deposition induced self-alignment (DISA) process step for a pyro
oxide film (borophosphoric silicon glass - BPSG) producing a
borderless contact. A generic RIE stop (Al2O3) is used over the
insulating film of Si3N4 . Fig. 5 shows the structure after a RIE
step which leaves oxide on top of the gates. Fig. 6 shows...