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Method for super capacitor stacking

IP.com Disclosure Number: IPCOM000100600D
Publication Date: 2005-Mar-15
Document File: 3 page(s) / 67K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for super capacitor stacking. Benefits include improved functionality.

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Method for super capacitor stacking

Disclosed is a method for super capacitor stacking. Benefits include improved functionality.

Background

      Conventionally, capacitors are placed on printed circuit boards (PCBs) and connected to the integrated circuit (IC) power supply. As board and component sizes shrink and functionality increases, an increasing number of capacitors are required within a minimal space.

      Super capacitors are thinner, lighter, and more compact than conventional capacitors (see Figure 1). Super capacitors have a simple input and output design. Two thin plates are placed in a fluid medium and sealed within an enclosure.

      Capacitors have been stacked in applications, such as dynamic random access memory (DRAM). Stacking has not been conventionally applied to super capacitors.

General description

      The disclosed method stacks super capacitors in a form factor that fits into an IC package or stand-alone component.

              The key elements of the method include:

•             Super capacitors

•             Stacking

•             Chip-scale capacitor

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to increasing capacitance within the extremely tight space of an IC package

Detailed description

      The disclosed method shrinks super capacitor enclosures to the size of package-level systems. Alternatively, the enclosures can be integrated within IC packages...