Browse Prior Art Database

Dual-Line Interrupt Scheme

IP.com Disclosure Number: IPCOM000100610D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Millas, RJ: AUTHOR [+2]

Abstract

This article describes a technique for use in a microprocessor system wherein the number of lines required to deliver interrupts and acknowledgements is reduced.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual-Line Interrupt Scheme

       This article describes a technique for use in a
microprocessor system wherein the number of lines required to deliver
interrupts and acknowledgements is reduced.

      In a typical microprocessor system, several interrupt lines are
used for multiple devices to interrupt.  Several more lines also are
used to acknowledge the various interrupts.

      A method is disclosed herein to reduce the number of lines
required to deliver interrupts and acknowledgements. Fig. 1 shows a
microprocessor controller using this dual-line interrupt scheme
(DLIS).  A serial input line SINT is an open collector line that
interrupting devices use to issue their interrupts.  A separate
serial output line SACK is used to acknowledge the interrupting
devices.

      The timing diagram shown in Fig. 2 illustrates how the DLIS
protocol functions.  Interrupts are issued by the interrupting
devices as pulses on the SINT line.  The SINT line is time-division
multiplexed such that each interrupting device has a preassigned time
slot during each cycle.  The same is true for the interrupt SACK
line.  The SACK line is also time-division multiplexed such that for
each interrupt time slot on the SINT line, a corresponding
acknowledgement time slot also exists on the SACK line.

      At the beginning of every cycle, a synchronization signal is
generated by the microprocessor controller over the SACK line.  This
synchronization signal is 1.5 time slot pulses in length.  This
signal is transmitted over the SACK line instead of the SINT line so
that the SINT line would not have to be bidirectional. Also, since
the SACK line is already an output line of the microproc...