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Generalized Lssd Boundary-Scan Design System

IP.com Disclosure Number: IPCOM000100614D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Bassett, RW: AUTHOR [+3]

Abstract

This article discloses a general level-sensitive scan design (LSSD) boundary-scan process and method that support reduced pin-count testing. A system designer may control the boundary-scan configuration on a pin-by-pin basis. Functional data paths are intercepted by boundary-scan cells located in the internal logic array. Each such cell may be either an LSSD shift register latch (SRL) or a special multiplexer-SRL (MUX-SRL, see the figure). Each latch may be either a functional system latch or a test-only latch. LSSD clock gating is permitted and is fully testable.

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Generalized Lssd Boundary-Scan Design System

       This article discloses a general level-sensitive scan
design (LSSD) boundary-scan process and method that support reduced
pin-count testing.  A system designer may control the boundary-scan
configuration on a pin-by-pin basis. Functional data paths are
intercepted by boundary-scan cells located in the internal logic
array.  Each such cell may be either an LSSD shift register latch
(SRL) or a special multiplexer-SRL (MUX-SRL, see the figure).  Each
latch may be either a functional system latch or a test-only latch.
LSSD clock gating is permitted and is fully testable.

      Reduced pin-count testing is test and stress of product using
testers with fewer fully-configured pin channels than the product has
signal input/outputs (I/Os). LSSD boundary-scan uses SRLs to
intercept functional data I/Os, allowing the product to be tested and
stressed while continuously contacting only the LSSD test-function
I/Os. The elements of the process are:
1. An I/O cell library containing: ;a. conventional drivers,
receivers, and common I/Os (CIOs) used for LSSD test-function pins.
b. conventional drivers, receivers, and CIOs used for data-func
 tion pins.  The data-function driver circuits are schematically
equivalent to test-function drivers but are represented to the design
automation process as distinct elements.  The data- function receiver
circuits incorporate a mandatory receiver- inhibit input signal whose
inhibiting value will force a fixed known value to the receiver
output regardless of the data input value.  The receiver-inhibit
signal is fed from a test-function input.
2. An internal logic cell library containing conventional LSSD SRLs
and a special MUX-SRL cell having the configur...