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Selectable Full Or Partial Swing Output Level Converter

IP.com Disclosure Number: IPCOM000100616D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Horel, TA: AUTHOR [+3]

Abstract

This circuit provides a means of selecting two pairs (four levels) of output voltage. A common BICMOS interface circuit selects a partial or full swing logic output.

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This is the abbreviated version, containing approximately 88% of the total text.

Selectable Full Or Partial Swing Output Level Converter

       This circuit provides a means of selecting two pairs
(four levels) of output voltage.  A common BICMOS interface circuit
selects a partial or full swing logic output.

      Referring to the figure above, a selection can be made between
a full swing from ground potential to high supply potential (VDD) or
a partial swing from, e.g., 0.8 volts above ground (GND) to 0.8 volts
below VDD.  As indicated, the circuit is comprised of four kinds of
circuit elements: driver, inverter, level selector, and voltage
reference.

      Two inverters provide proper interface levels to the level
selector.  A first inverter, having input Select and output at node
A3, is comprised of P-channel transistor 1 and N-channel transistor
2.  A second inverter having input from node A2 and output at node A4
is comprised of transistors 3 and 4.  The level selector is comprised
of transistors 5 through 12.  Bipolar transistors 13 and 14 and
resistor R1 are used to establish two reference voltages (E1) and
(E0) on nodes A5 and A6.  The value of resistor R1 is selected to
limit current flowing through transistors 13, 14 and resistor R1 and
to cause a voltage drop of (E1) = 0.8 volts below VDD and (E0) =
0.8 volts above GND at nodes A5 and A6, respectively.

      The table above shows the conduction state of each device and
the output voltage at Out for each combination of input levels at
Select and Data IN.

     ...