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Browse Prior Art Database

Voltage Regulator Power Reduction

IP.com Disclosure Number: IPCOM000100618D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-15
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Sartwell, AL: AUTHOR [+2]

Abstract

A voltage regulator circuit modification is shown for maintaining constant voltage while reducing standby current.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Voltage Regulator Power Reduction

       A voltage regulator circuit modification is shown for
maintaining constant voltage while reducing standby current.

      Many VLSI chips currently in use require voltage regulation for
chip reliability and system compatibility. To meet demands on
performance, a voltage regulator must be able to respond quickly to
changes in load current. This requires large devices and consequently
large standby currents, increasing circuit power. A method is shown
for reducing standby power without sacrificing regulator response
when it is needed. The voltage output during standby is the same as
that during full power operation. The standby state supplies leakage
current to the chip, thus maintaining voltage levels on chip
circuits, such as bit lines and sense systems.

      A typical N channel output CMOS regulator is shown in Fig. 1.
Devices T1 and T2 are P channel FETs and T3, T4, T5 and T6 are
N channel FETs. The circuit compares a reference voltage to the
output voltage and the current set by T5 is normally equally
distributed through T3 and T4. If Vout drops below Vref, T4 starts to
turn off.  Node B rises, turning T6 on harder. At the same time, node
C drops while T5 is still sinking the same current. This increases
the drive on T3, pulling node A down and turning T2 on harder,
further increasing the drive on T6 until Vout reaches Vref and the
currents through T3 and T4 are again equal.

      Fig. 2 shows a modified volta...