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Method for a top-die wire profile and a second bond position for a 4-die stacked CSP

IP.com Disclosure Number: IPCOM000100624D
Publication Date: 2005-Mar-15
Document File: 3 page(s) / 249K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a top-die wire profile and a second bond position for a 4-die stacked chip-scale package (CSP). Benefits include improved functionality, improved performance, and improved reliability.

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Method for a top-die wire profile and a second bond position for a 4-die stacked CSP

Disclosed is a method for a top-die wire profile and a second bond position for a 4-die stacked chip-scale package (CSP). Benefits include improved functionality, improved performance, and improved reliability.

Background

              Unexpected issues in the assembly process, such as wire cutting after the package sawing process, due to excessive wire pay-out and subsequent wire sweeping (see Figure 1). This problem is conventionally solved by sample X-ray inspection after the molding process and external visual inspection (EVI) before packing to detect wire sweeping and external defects, such as wire cuts (see Figure 2).

Description

      The disclosed method is a top-die wire profile and a second bond position for 4-die stacked CSPs (see Figure 3). The wire length is shorter. Wire pay-out and sweeping prevents the wire from cutting into the multichip stacked CSP (see Figure 4).

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing a top-die wire profile and parallel bonding for a 4‑die stacked CSP

•             Improved performance and reliability due to shortening the wire length

•             Improved reliability due to reducing wire sweeping, pay-out and wire cutting

Fig. 1

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Fig. 3

Fig. 4

Disclosed anonymously