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Method for manufacturing a coreless multilayer substrate

IP.com Disclosure Number: IPCOM000100639D
Publication Date: 2005-Mar-16
Document File: 5 page(s) / 116K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for manufacturing a coreless multilayer substrate. Benefits include improved throughput and improved cost effectiveness.

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Method for manufacturing a coreless multilayer substrate

 

Disclosed is a method for manufacturing a coreless multilayer substrate. Benefits include improved throughput and improved cost effectiveness.

Background

              In substrate manufacturing, a continuing goal is to provide low cost, high reliability, and high density wiring. As a result, a build-up technique has been developed for stacking thin layers that are alternatively insulative and conductive. Additionally, conductive via holes interconnect the conductive layers on a core substrate. The number of layers built up can be further increased to more than ten or twenty layers to meet the requirements of some applications (see Figure 1).

      A multilayer substrate manufactured with build-up process technology has a long fabrication time because the layer count is built up gradually by forming each layer on the previously formed layer. The through-put time must be reduced but no conventional solution exists.

      Alternatively, multilayer substrates can be manufactured using a lamination process. The stack of each layer is held with a press or vacuum laminator and subjected to pressure and heat for a specified time and pressure. This conventional stack-up process requires a binder material so that adhesion of each layer is achieved.

General description

      The disclosed method is the fabrication of a coreless multilayer substrate. The conventional substrate manufacturing process can be utilized provided the availability of dielectric material is ensured. The dielectric material must maintain its adhesion while the opening microvia or through hole can be created in the dielectric layer. Adequate stiffness must be created during the process and after lamination.

              The key elements of the method include:

•             Coreless structure

•             Use of temporally base film to form a single circuit layer in the process

•             Stacking and laminating each single layer and interconnecting between the two layers through a preformed via hole with copper plating

Advantages

              The disclosed method provides advantages, including:

•             Improved throughput due to shortening the fabrication time because each substrate layer is formed simultaneously

•             Improved cost effectiveness due eliminating the core material

Detailed description

              The disclosed method is the fabrication of a coreless multilayer substrate where each substrate layer is formed simultaneous...