Browse Prior Art Database

Very Fast Two-Stage NOR Decoder

IP.com Disclosure Number: IPCOM000100649D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+5]

Abstract

The disclosure describes an innovative two-stage NOR decoder. As the sense amplifier, the decoder is also a block source of delays in the critical path of the access of memories. It has to be fast and have low power consumption. The circuit of the disclosed decoder makes a very good trade-off between speed and power. It has a good density and especially allows an easy physical expansion of the number of bit addresses.

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Very Fast Two-Stage NOR Decoder

       The disclosure describes an innovative two-stage NOR
decoder. As the sense amplifier, the decoder is also a block source
of delays in the critical path of the access of memories. It has to
be fast and have low power consumption. The circuit of the disclosed
decoder makes a very good trade-off between speed and power. It has a
good density and especially allows an easy physical expansion of the
number of bit addresses.

      The circuit is shown in Fig. 1. The first stage makes a NOR
function of the true/complement inputs of the addresses, and the
second stage is a multiplexer unit decoding the last bit address.

      The NOR function is done ONLY with the NFET devices. The PFET
device pulls up the NOR node (A) to the supply voltage VDD, decoding
A0 to An-1 bit addresses if all the true/complement inputs are
grounded.  On the contrary, in all the known NOR decoders which have
one or more true/complement inputs at the high level, both the NFET
devices and the VERY FAST TWO-STAGE NOR DECODER - Continued PFET
device are ON. In order to decode only one address, the PFET device
is designed to be smaller than the NFET device, keeping the NOR node
(A) in the low level. Consequently, the Set Word Decoder (SWD) signal
quickly decodes only one of them.

      Fig. 2 shows the timings between the different signals.

      The multiplexer decodes one world line of two. As a result, the
power comsumption is divided by a facto...