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Formation of Filled Via Substrate

IP.com Disclosure Number: IPCOM000100654D
Publication Date: 2005-Mar-16
Document File: 4 page(s) / 29K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for forming filled vias by adding a tapering step after the via hole formation step. Benefits include a solution that provides a more stable and reliable interconnection.

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Formation of Filled Via Substrate

Disclosed is a method for forming filled vias by adding a tapering step after the via hole formation step. Benefits include a solution that provides a more stable and reliable interconnection.

Background

Currently, there is a need to have a low cost interconnection between the top and bottom electrode in a double-sided, copper-laminated substrate with a filled via structure (see Figure 1). To accomplish this, through holes and blind vias are plugged by filled via copper plating, using conventional PCB technology. Since the holes must be filled without voids, the plating process control is more difficult than the normal plating method, and therefore it requires a longer throughput.

Other methods, including metal implantation and riveting, are used for making low-cost, high-throughput interconnections; however, the reliability and electrical resistance stability of these methods are not sufficient for IC packaging use.

General Description

In the disclosed method, the components are: a double-sided, a copper-laminated LCP (Liquid Crystal Polymer) substrate, a tapered via hole, a metal implant, and the top and bottom via lands which are made by riveting (see Figure 2). The metal-to-metal contact area enlargement improves contact resistance stability among the top and bottom electrode and the implanted metal.    

Figure 3 shows the process flow of the disclosed method. During the first step, the LCP substrate is prepared. A substrate dielectr...