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New Architecture of Transparent Refresh for Ram

IP.com Disclosure Number: IPCOM000100658D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 83K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+4]

Abstract

The purpose of this article is to describe the principle of a transparent refresh operation and its logical implementation. It takes place in Random Access Memories (RAMs) which use 4-device cells (4D-Cells). Fig. 1 shows a comparison of 4D-cell with a 6D-cell. The 4D-cell has the same functionality as the 6D-cell, but in a 6D-cell, 2 PFET devices load the two nodes of the cell; in the case of the 4D-cell, the high voltage node could be pulled down by leakage currents due to diffusion current, sub-threshold current or any parasitic current. Assuming T3 is ON and holds the low voltage node A at the low level, in the 6D-cell, T6 is ON and holds the node B at the high level when T4 is OFF, while in the 4D cell, the node B is floating at the high level when T4 is OFF.

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New Architecture of Transparent Refresh for Ram

       The purpose of this article is to describe the principle
of a transparent refresh operation and its logical implementation. It
takes place in Random Access Memories (RAMs) which use 4-device cells
(4D-Cells).  Fig. 1 shows a comparison of 4D-cell with a 6D-cell. The
4D-cell has the same functionality as the 6D-cell, but in a 6D-cell,
2 PFET devices load the two nodes of the cell; in the case of the
4D-cell, the high voltage node could be pulled down by leakage
currents due to diffusion current, sub-threshold current or any
parasitic current. Assuming T3 is ON and holds the low voltage node A
at the low level, in the 6D-cell, T6 is ON and holds the node B
at the high level when T4 is OFF, while in the 4D cell, the node
B is floating at the high level when T4 is OFF. A refresh operation
is therefore needed to maintain the storage of the information in the
cell.

      The Refresh scheme which is described in this article is
implemented within the RAM. RAMs using 4D-cells with this new
architecture of transparent refresh behave like static RAMs for the
user. But from the internal view side, it is a quasi-static behavior
because any Read/Write operation is followed by at least one refresh
operation. In order to perform these two successive operations, a
minimum cycle time (Tc min) has to be specified.  With an
asynchronous user clock, the internal refresh operation is performed
as long as the user does not need to access the RAM as apparent from
Fig. 2. The major advantage of...