Browse Prior Art Database

Full-Swing, Ground-Level-Shifted BiCMOS Circuits

IP.com Disclosure Number: IPCOM000100663D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Chen, CL: AUTHOR

Abstract

Disclosed is a level-shifted NPN-only BiCMOS circuit which has output levels compatible with that of CMOS circuits. (Image Omitted) The level-shifting scheme for CMOS circuits is shown in Fig. 1(a). The Vh and Vl supply rails for CMOS circuits are offset by Vbe (Z0.8 V), each with respect to the supplies Vdd and Vss, respectively. After the Vbe reduction of the bipolar transistors, the output swing of a BiCMOS circuit matches the CMOS supply levels, as shown in Fig. 1(b). Thus, the CMOS-like noise margin and overdrive voltage can be achieved. The Vbe shift can be implemented simply by an NPN transistor connected as a diode, or by a more complex voltage regulator circuitry. For a single 5 V Vdd supply and grounded Vss, the Vh and Vl for CMOS circuits are about 4.2 V and 0.8 V, respectively.

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Full-Swing, Ground-Level-Shifted BiCMOS Circuits

       Disclosed is a level-shifted NPN-only BiCMOS circuit
which has output levels compatible with that of CMOS circuits.

                            (Image Omitted)

 The
level-shifting scheme for CMOS circuits is shown in Fig. 1(a).  The
Vh and Vl supply rails for CMOS circuits are offset by Vbe (Z0.8 V),
each with respect to the supplies Vdd and Vss, respectively.  After
the Vbe reduction of the bipolar transistors, the output swing of a
BiCMOS circuit matches the CMOS supply levels, as shown in Fig. 1(b).
Thus, the CMOS-like noise margin and overdrive voltage can be
achieved.  The Vbe shift can be implemented simply by an NPN
transistor connected as a diode, or by a more complex voltage
regulator circuitry.  For a single 5 V Vdd supply and grounded Vss,
the Vh and Vl for CMOS circuits are about 4.2 V and 0.8 V,
respectively.  The net voltage across CMOS circuits is then (Vh-Vl),
i.e., 3.4 V, which is close to the scaled-down supply for 0.5 mm CMOS
devices.

      Fig. 2 shows the disclosed ground-level-shifted NPN-only BiCMOS
circuit.  Details of the circuit operation is described in the
following.  For a pull-up operation, the pull-up NPN transistor Qu is
driven directly by the CMOS output and operated as an
emitter-follower.  For a pull-down operation, a large P-channel FET
P1 inverts the CMOS output and acts as a switch between the base and
collector of the pull-down NPN tra...