Browse Prior Art Database

System Partitioning Which Allows 2 Or 4 Data-Cache Logic Chip Configurations

IP.com Disclosure Number: IPCOM000100675D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Hardell, WR: AUTHOR [+3]

Abstract

The microprocessor chips have been designed such that two distinct system configurations can be created from the same module part numbers. By adding additional function to the SCU, FXU and DCU, and rewiring a planar to dot busses, a lower performance and cost microprocessor system can be created with only two data-cache modules instead of four in the higher performance microprocessor system.

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System Partitioning Which Allows 2 Or 4 Data-Cache Logic Chip Configurations

       The microprocessor chips have been designed such that two
distinct system configurations can be created from the same module
part numbers.  By adding additional function to the SCU, FXU and DCU,
and rewiring a planar to dot busses, a lower performance and cost
microprocessor system can be created with only two data-cache modules
instead of four in the higher performance microprocessor system.

      A high-end system configuration has a 64K byte 4-way set
associative data-cache divided between four data-cache modules.  The
data cache modules also have additional logic to support memory bit
steering, ECC generation and correction, buffers to service
instruction cache reloads and buffers to support Direct Memory Access
(DMA) operations. Additional logic has been added so that in a
lower-cost 2-data- cache version, twice as much buffering is
available to service I-cache misses of the same 64-byte line size.
In the high-end configuration, the modules have extra buffer space
that in the future could be used for I-cache prefetching.

      In the higher performance system there is a dedicated bus from
the D-cache modules to the I-cache modules to service I-cache
reloads.  In the low-end system, the planar is wired such that the
I-cache is dotting onto the SIO bus for this data.  The SCU, DCU and
FXU have mode pins tied on the planar to identify which system is
configured.  This mode pin on the SCU determines the manner in which
the SCU arbitrations for the SIO bus and services I-cache reloads.
The mode pin on the data-cache determines the buffering and control
schemes for I-cache reloads, D-cache relo...