Browse Prior Art Database

Logic Synchronizer Circuit/Clock Generator

IP.com Disclosure Number: IPCOM000100676D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Kinter, HB: AUTHOR

Abstract

Disclosed is a circuit designed to allow the attachment of a microprocessor to an existing Arbitration Control circuit. The uniqueness is the manner in which a faster microprocessor is synchronized to the Arbitration Control circuit, originally designed to run with a much slower microprocessor.

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This is the abbreviated version, containing approximately 52% of the total text.

Logic Synchronizer Circuit/Clock Generator

       Disclosed is a circuit designed to allow the attachment
of a microprocessor to an existing Arbitration Control circuit. The
uniqueness is the manner in which a faster microprocessor is
synchronized to the Arbitration Control circuit, originally designed
to run with a much slower microprocessor.

      Fig. 1 shows how the disclosed circuit is related and used in
this application.  There are two functional areas competing for the
SHARED RESOURCE, the 80C186 microprocessor and Function A, which
could be another microprocessor or control logic.  The SHARED
RESOURCE, static memory in this application, has only one input
(address) and one output (data), which must be multiplexed between
the 80C186 and Function A.  It is the Arbitration Control that
monitors and grants access to the SHARED RESOURCE in an orderly
manner. It does this by using the 80C186 CLKOUT SYNC/2 to generate a
clocking system.

      As stated above, the Arbitration Control circuit already
existed but was designed to run at a speed 33% slower than this
application required.  Attempting to run the Arbitration Control at
this higher microprocessor speed resulted in errors during any
Function A operation.

      The SYNC CKT was designed to eliminate the above problem and
allow the use of existing Arbitration Control logic.  It provides:
   1.  A means of synchronizing an asynchronous logic function
(Function A) and an 80C186 microprocessor by manipulating the
microprocessor clock driving the arbitration control.
   2.  An acceptable clock period to maintain proper operation of the
Arbitration Controls.  The 80C186 CLKOUT signal is divided by two and
synchronized before input to the Arbitration Controls.

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