Browse Prior Art Database

Simultaneous Register Read Access

IP.com Disclosure Number: IPCOM000100690D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Fleurbaaij, JM: AUTHOR

Abstract

This article describes a register scheme for processors that speeds up processor instruction execution by allowing two different registers to be read simultaneously.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 86% of the total text.

Simultaneous Register Read Access

       This article describes a register scheme for processors
that speeds up processor instruction execution by allowing two
different registers to be read simultaneously.

      As can be seen from the schematic in the figure, there are two
duplicate LSR (Local Storage Register) sets, the M-LSRs and the
C-LSRs.
Each set has 16 registers, each 8 bits wide.  Both sets have the same
ENABLE and WRITE signals.  The data to both register sets is the same
REG DATA IN BUS.  Also, both register sets have the same 4 possible
address sources, ADDRESS FIELD 1, 2, 3 and 4.

      The M-LSRs are addressed via the M-REG Address Multiplexer,
which provides one 6-bit address to the M-REG set.  In the same
manner, the C-LSRs are addressed via the C-REG Address Multiplexer.
Address selection is done with the select lines, M-REG ADDR SEL and
C-REG ADDR SEL.

      During a register write, both address multiplexers select the
same address source and, so, both register sets are written with the
same data.  This means that both register sets will always contain
the same data.

      During a register read each address multiplexer can select one
of the four address sources.  As a result, the same or different
registers can be read from the M and C register sets at the same
time.

      By gating the two register set output busses (the M-REG BUS and
the C-REG BUS) to the two inputs of an ALU (Arithmetic Logic Unit),
arithmetic and l...