Browse Prior Art Database

Flexible Address Pattern Generator for a Memory Tester

IP.com Disclosure Number: IPCOM000100695D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 103K

Publishing Venue

IBM

Related People

Kam, PK: AUTHOR

Abstract

This article describes a scheme for generating address patterns used in a memory tester. Instead of using up/down counters to generate linear incremental or decremental address patterns, RAMs divided into segments are used to generate all the algorithmic patterns that counters can do. Furthermore, these RAMs can be programmed to do address weight changing in real test time, row and column multiplexing, non-linear increment, decrement or even random patterns without additional logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Flexible Address Pattern Generator for a Memory Tester

       This article describes a scheme for generating address
patterns used in a memory tester.  Instead of using up/down counters
to generate linear incremental or decremental address patterns, RAMs
divided into segments are used to generate all the algorithmic
patterns that counters can do. Furthermore, these RAMs can be
programmed to do address weight changing in real test time, row and
column multiplexing, non-linear increment, decrement or even random
patterns without additional logic.

      Implementation is illustrated in the figure.  It shows only
four segments for simplicity purposes.  Each segment consists of a
RAM and an associated address counter. Predetermined address patterns
will be loaded into the RAM by a system controller.  Each unique
pattern (such as binary increment or decrement) will occupy a
selection of the RAM. A starting address which points to those unique
patterns will be loaded into the address counter in each test.

      The width of the RAM is not important.  A wider RAM takes more
locations to implement some unique patterns (e.g., it requires 256
locations for a linear incremental/decremental pattern for a width of
8 bits; it takes 16 locations for 4 bits, but it requires two 4-bit
segments to provide 8 address lines to the product).  The segment RAM
also contains a control bit which serves two purposes:  to reset its
address counter to the starting address and to form one of the
address bits to the 'segment enable control' RAM.

      The segment control RAM has a bit for each segment, a bit of
'1' allows that segment to advance; a '0' puts that segment on hold.
This RAM is divided into many sections; each section is associated
with each address pattern stored in the segment RAMs.  The locations
required for each section equal 2 to the power of the number of
segments.  The system controller selects which section to be used in
a test.  This RAM is also preloaded by the system controller.

      The following example illustrates how to use the address
pattern generator shown in the figure.

      A product requires 8 column and 8 row address lines. The
assignment is:  segment 0 to row 0 to 3, segment 1 to row 4 to
7, segment 2 to column 0 to 3, segment 3 to column 4 to 7.
Segment RAMs 0 to 3 will be preloaded with these patterns:
      location   bits 3 2 1 0  control bit  count of
          0           0 0 0 0     0           0
          1           0 0 0 1     0           1
          2           0 0 1 0     0           2
                        ..
                        ..
          F           1 1 1 1     1          15  control bit
                                            ...