Browse Prior Art Database

LSSD Boundary-Scan Design System for Reduced Pin-Count Testing

IP.com Disclosure Number: IPCOM000100697D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Bassett, RW: AUTHOR [+3]

Abstract

This article discloses a level-sensitive scan design (LSSD) boundary-scan process and method that support reduced pin-count testing. Boundary-scan latches are included in input/output (I/O) cells with minimal impact on density and performance of the functional design. These latches are connected in series with the functional data paths and are transparent (i.e., flushed through) in normal operation.

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LSSD Boundary-Scan Design System for Reduced Pin-Count Testing

       This article discloses a level-sensitive scan design
(LSSD) boundary-scan process and method that support reduced
pin-count testing.  Boundary-scan latches are included in
input/output (I/O) cells with minimal impact on density and
performance of the functional design.  These latches are connected in
series with the functional data paths and are transparent (i.e.,
flushed through) in normal operation.

      Reduced pin-count testing is test and stress of product using
testers with fewer fully-configured pin channels than the product has
signal I/Os.  LSSD boundary scan uses shift register latches (SRLs)
to intercept functional data I/Os, allowing product to be tested and
stressed while continuously contacting only LSSD test-function I/Os.
The elements of the process are:
1. An I/O cell library containing:
   a. conventional drivers, receivers, and common I/Os (CIOs) used
for test-function pins;
      b. drivers, receivers, and CIOs with series latches used for
data-function pins (see Fig. 1);
      c. boundary-scan buffer cells to distribute clock signals to
the boundary latches and to begin/end the boundary-scan shift
register.
2. A chip design automation method that:
   a. assigns a subset of I/O sockets as test-function I/O sockets
and the full set of I/O sockets as data I/O sockets;
      b. assigns either a data I/O placement attribute or a test-func
       tion...