Browse Prior Art Database

Wait State Control Circuit

IP.com Disclosure Number: IPCOM000100698D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Kinter, HB: AUTHOR

Abstract

Disclosed is a method designed to allow use of existing logic functions in a microprocessor control system running 50% faster than the original control system these functions were designed for. This is accomplished by adding logic to control and generate wait state conditions for the microprocessor. A logic block diagram is shown in Fig. 1 and a Timing diagram in Fig. 2.

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Wait State Control Circuit

       Disclosed is a method designed to allow use of existing
logic functions in a microprocessor control system running 50% faster
than the original control system these functions were designed for.
This is accomplished by adding logic to control and generate wait
state conditions for the microprocessor.  A logic block diagram is
shown in Fig. 1 and a Timing diagram in Fig. 2.

      Several functions required assistance when running at a faster
microprocessor speed.  In Fig. 1 they are identified as 186 UCS, 186
PCS3, RAM CD MEM SEL and 186 PCS5.  The logic function is the same
for all signals; the only difference is the value the SHF REG is
allowed to reach. The uniqueness of this disclosure is:
   1.  It allows use of an existing functional design with a faster
microprocessor, thus preventing a redesign of the function.
   2.  This design extends the usefulness of older functional designs
by adding hardware assist to the microprocessor internal wait state
controls.

      Referring to Figs. 1 and 2, the sequence of events for a 186
PCS5 operation is described.  This operation generates the longest
wait condition.

      At end of 186 ALE, the LCH block is set on, indicated by the
fall of the ARDY signal.  This signal is fed to the microprocessor
ready controls and de-activates or suspends its operation, adds wait
states and also enables the operation the SHF REG by putting a logic
'1' at the A&B inputs.  The 186 C...