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Phase-Locked Loop Protocol Scheme for a Contaminated Synchronization Field

IP.com Disclosure Number: IPCOM000100701D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Dimitri, K: AUTHOR [+3]

Abstract

Disclosed is a scheme that is capable of putting the Phase-Locked Loop (PLL) in lock and in synch with the last byte of the synchronization field even if that field had become contaminated at a later time, assuming that the sync field was written in a gross defect-free area at initial format.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Phase-Locked Loop Protocol Scheme for a Contaminated Synchronization Field

       Disclosed is a scheme that is capable of putting the
Phase-Locked Loop (PLL) in lock and in synch with the last byte of
the synchronization field even if that field had become contaminated
at a later time, assuming that the sync field was written in a gross
defect-free area at initial format.

      In a virtually defect-free media, first predetermined bytes
(usually 80%) of the sync field are used for the high gain mode of
the PLL in order to establish frequency and phase lock.  The PLL is
switched to the low gain mode at the end portion of that field in
order to stabilize sync acquisition, by slowing down the PLL acquire
rate.  The remaining 20% of the field is used to settle any transient
switching and prepare the PLL for data reading.

      In media where defects could grow at a later time after
initialization, it will be advantageous to be able to switch the PLL
to low gain once it has acquire lock, without waiting for the
predetermined fix high gain time to expire. This can be achieved with
the following design steps and scheme:
1.   Proper choice of filter components to achieve quick phase and
frequency acquired in high gain mode of the PLL.  Simulation was used
in order to determine how many defect-free bytes it would take the
PLL in high gain to acquire synch, assuming it started from an
initial worst-case phase error.  See Fig. 1.
2.   Circuitry means of monitor...