Browse Prior Art Database

Two-Level DMA From Channels to Main Store

IP.com Disclosure Number: IPCOM000100710D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Irwin, JW: AUTHOR

Abstract

A method is described for a two-level DMA from a number of I/O channels to a processor main store through a concentrator with special facilities to merge error status detected in channel and concentrator into a common error word.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Two-Level DMA From Channels to Main Store

       A method is described for a two-level DMA from a number
of I/O channels to a processor main store through a concentrator with
special facilities to merge error status detected in channel and
concentrator into a common error word.

      The processor memory bus (see the figure) is a wide, very high
bandwidth bus which can serve a number of I/O channels.  The DMA
buses (two depicted) are narrow, with bandwidth adequate only for the
demands of a single channel. Buffers in the concentrator match the
data rates of the buses.

      Programmed I/O (PIO) commands to the channels through the
processor and memory bus specify the direction of the DMA transfer,
and a list of addresses and lengths of data segments (scatter/gather
list).  PIO commands are routed down the distributed control bus and
latched in the selected I/O channel.  The channels then split up the
scatter-gather list in whatever sequence best matches the media and
are able to retransfer portions in error or reorder the transfer
sequence for improved performance.

      The I/O channels are default masters of the DMA buses and
initiate DMA transfer by sending a multibyte message to the
concentrator identifying the direction, target address, and length of
transfer.  The channel then relinquishes control of the DMA bus and
allows the concentrator to be bus master until the data is
transferred.

      If either unit detects an error during DMA tran...