Browse Prior Art Database

Serial Interface for Electronic Diagnostics

IP.com Disclosure Number: IPCOM000100717D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 7 page(s) / 318K

Publishing Venue

IBM

Related People

Marquart, DW: AUTHOR

Abstract

A service processor connects to a level-sensitive scan design (LSSD) interface of a card containing LSSD logic. There are one or multiple scan rings on the logic card. This requires several scan ring select signals and corresponding scan-in and scan-out signals, as well as control signals to control clocks other than the scan clocks, signals to put the logic in a state to be scanned, and the LSSD scan clocks themselves. This results in a large number of signals. In many packaging schemes, pins are at a premium and as few as possible should be used for service purposes. The described interface and architecture addresses this problem by reducing the number of I/O pins required in packaging.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 20% of the total text.

Serial Interface for Electronic Diagnostics

       A service processor connects to a level-sensitive scan
design (LSSD) interface of a card containing LSSD logic. There are
one or multiple scan rings on the logic card. This requires several
scan ring select signals and corresponding scan-in and scan-out
signals, as well as control signals to control clocks other than the
scan clocks, signals to put the logic in a state to be scanned, and
the LSSD scan clocks themselves.  This results in a large number of
signals.  In many packaging schemes, pins are at a premium and as few
as possible should be used for service purposes.  The described
interface and architecture addresses this problem by reducing the
number of I/O pins required in packaging.

      Multiple scan rings are served by one scan ring connection and
a few additional controls.  The single scan ring connection connects
to a set of control logic in the card or subset of the logic to
be scanned.  This scan control logic in turn connects to the scan
rings it is to control.  Fig. 1 shows that the interface to the scan
control logic comprises:
      -  a scan-in line
      -  a scan-out line
      -  an LSSD A clock
      -  an LSSD B clock
      -  a select line which addresses a logic card or subset
         to scan (target unit)
      -  a control mode line which indicates that control
         information is being scanned
      -  a scan mode line which indicates that logic other
         than the scan control is being scanned.

      The scan-in, scan-out, and LSSD A and B clocks are exactly like
the general LSSD scan mechanism.  The select line selects which card
or subset (out of many possible cards or subsets) is selected for
scanning.

      The control mode line selects the control register for
scanning.  After scanning is complete and the control mode line is
deactivated, the information from the control register is transferred
to other scan control registers in the control logic.  These other
registers control scanning and other functions in the rest of the
target unit.

      The scan mode line indicates that scanning is to scan other
LSSD rings than the control register.  The scan path on the card is
selected by the value of the control registers in the control logic;
these registers must be set via control register scanning before scan
mode is used.

      The scan rings on each target unit are controlled by the scan
control logic on that target unit.  The central controller sets the
controls by scanning the scan control logic's control register.  If
the central controller needs to scan a particular scan ring on a
target unit, the central controller selects the scan ring by setting
the scan ring select register in the scan control logic on the target
unit to select that scan ring, stopping the functional clocks and
further manipulation.  After all setup is completed in t...