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On-Chip Receiver Featuring Fall-Through Radiation-Hardened Latching

IP.com Disclosure Number: IPCOM000100722D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Ciraula, MK: AUTHOR [+3]

Abstract

Many VLSI chips can make use of fall-through latches on their input signals, particularly in memory application, to aid in interleaving in system environments. In standard products, this is easily accomplished by putting a simple feedback latch in the input path and will cause little or no access penalty due to the nature of the latch circuit. However, in radiation-hardened chips, these latches are susceptible to Single Event Upset (SEU) that may change the state of the data stored in the latch circuit. Therefore, radiation-hardened (SEU immune) latches must replace their non-hardened counterparts. However, the radiation-hardened versions are inherently slower than non-hardened circuits and will slow the performance of the On Chip Receiver (OCR) and, thus, increase access time of the chip.

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On-Chip Receiver Featuring Fall-Through Radiation-Hardened Latching

       Many VLSI chips can make use of fall-through latches on
their input signals, particularly in memory application, to aid in
interleaving in system environments.  In standard products, this is
easily accomplished by putting a simple feedback latch in the input
path and will cause little or no access penalty due to the nature of
the latch circuit. However, in radiation-hardened chips, these
latches are susceptible to Single Event Upset (SEU) that may change
the state of the data stored in the latch circuit.  Therefore,
radiation-hardened (SEU immune) latches must replace their
non-hardened counterparts.  However, the radiation-hardened versions
are inherently slower than non-hardened circuits and will slow the
performance of the On Chip Receiver (OCR) and, thus, increase access
time of the chip.  The circuit disclosed in this article describes a
radiation-hardened OCR with the fall-through latch that causes
little, if any, access penalty.

      A diagram of a simple feedback latch is shown in Fig. 1.  The
radiation hardened counterpart is shown in Fig. 2. The addition of
resistors R1 and R2 in the radiation-hardened version causes two main
effects:  (1) it protects the latch against SEU, and (2) it forces
the write time of the latch to increase greatly due to the RC network
produced.  Therefore, just placing the radiation-hardened latch in
the circuit will increase the delay through the OCR if not done
correctly.  This can be seen in the block diagram of Fig. 3 which
shows the general form of the circuit required.  Note that the latch
is in the data path through the OCR and, therefore, the resistors in
the radiation-hardened latch will increase the delay through the OCR
from the input to output.  This time, as previously stated, can be
much greater than in the non- hardened version.

      A diagram of the new OCR is shown in Fig. 4.  The delay time
through the new OCR will not differ significantly from a non-hard...