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Optimum Performance in Mixed Memory Speed Environment

IP.com Disclosure Number: IPCOM000100723D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Lakkis, EJ: AUTHOR

Abstract

The control and access of each main store (MS) card in a system is individualized, and fast MS cards are not forced to run at a speed of slower cards. This individualization is accomplished with simple control circuitry which is initialized at initial program load (IPL). The core of the circuitry is an array of memory configuration registers (MCRs), with one MCR for each MS card slot in the system. If the system implementation allows for n MS cards, then there must be at least n MCRs in the array. At IPL and before attempting any MS accesses, the system needs to know the size and type, and the physical data of the MS cards so they are properly configured, addressed, and controlled. This vital information is captured by polling one MS card at a time and storing the data in the corresponding MCR.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Optimum Performance in Mixed Memory Speed Environment

       The control and access of each main store (MS) card in a
system is individualized, and fast MS cards are not forced to run at
a speed of slower cards.  This individualization is accomplished with
simple control circuitry which is initialized at initial program load
(IPL).  The core of the circuitry is an array of memory configuration
registers (MCRs), with one MCR for each MS card slot in the system.
If the system implementation allows for n MS cards, then there must
be at least n MCRs in the array.  At IPL and before attempting any MS
accesses, the system needs to know the size and type, and the
physical data of the MS cards so they are properly configured,
addressed, and controlled.  This vital information is captured by
polling one MS card at a time and storing the data in the
corresponding MCR.

      The MS control unit in a computer system usually receives a
real address translated from a virtual address by a virtual address
translation scheme.  The real address represents the maximum physical
address space allowed by the system's organization.  The physical MS
installed needs not be as large as the address space, hence the need
to map the real address into a physical address.  This map is
performed by a physical address generator (see Fig 1).  The address
generator maps the real address into a physical address based on the
information contained in the MCR.  The MCR contains data describing...