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Electrically Enhanced Trench Isolation for Ulsi Applications

IP.com Disclosure Number: IPCOM000100726D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Conti, R: AUTHOR [+4]

Abstract

Deep trench structures are commonly being used in semiconductor devices today for either isolation purposes or forming large capacitors. Significant increasing in packing density is thus realized. However, due to the inherent oxide charges existing at the interfaces of the oxide liners and trench sidewalls, undesirable n-type inversion layers were constantly measured (1). Such inversion layers have caused leakage between adjacent n-channels as well as weakening of the MOS latch-up resistance (2).

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Electrically Enhanced Trench Isolation for Ulsi Applications

       Deep trench structures are commonly being used in
semiconductor devices today for either isolation purposes or forming
large capacitors.  Significant increasing in packing density is thus
realized.  However, due to the inherent oxide charges existing at the
interfaces of the oxide liners and trench sidewalls, undesirable
n-type inversion layers were constantly measured (1).  Such inversion
layers have caused leakage between adjacent n-channels as well as
weakening of the MOS latch-up resistance (2).

      A technique is proposed to form Al2O3 liners at trench
sidewalls butting to the p-epi zones and thermal oxide liner to
n-well zones.  After a proper annealing cycle, the Al2O3 sidewall
tends to induce a P-layer surface while SiO2 sidewall an N-layer.
This phenomenon was verified by the experimental data and agreed with
the results indicated in the literature (3).  In such arrangement, as
shown in the figures, all the n-channels are electrically isolated by
the reversed biased p-epi and p-sidewalls.  Similarly, p-channels are
isolated by the reversed biased n-well and n-sidewalls.

      Furthermore, the epi defects are removed during the formation
of the oxide liners.  Any leakage due to defects is entirely
eliminated.  Therefore, channels are allowed to be butted to the
trench sidewalls and higher density of device packing be achieved.

      References
(1) R. D. Rung, "Trench Is...