Browse Prior Art Database

High Density, Zero Power CMOS Redundancy Circuit

IP.com Disclosure Number: IPCOM000100728D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Durham, CM: AUTHOR [+3]

Abstract

This article describes a new circuit which provides a smaller, easier means to program redundant word or bit lines for memory chips. In addition, it retains zero power of previous state-of-the-art chip designs.

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High Density, Zero Power CMOS Redundancy Circuit

       This article describes a new circuit which provides a
smaller, easier means to program redundant word or bit lines for
memory chips.  In addition, it retains zero power of previous
state-of-the-art chip designs.

      Memory chip yield can be improved through redundancy; by the
inclusion of reprogrammable redundant word and bit lines in the chip,
bad word and bit lines can easily be replaced.  Fuses provide the
means to deselect a bad word or bit line and replace it with a
redundant wordline.  Previous redundancy schemes have generally been
complicated and required two fuses per address bit.  The circuit
described in this article describes a new redundancy scheme that
requires one fuse per address and, because it is completely static
and CMOS, requires very low power.

      Fig. 1 shows the circuit when the fuse is not blown. In this
condition, repair is tied high via the fuse, and repair will be
forced low.  When the fuse is blown, the circuit will appear as shown
in Fig.  2, where repair will be low, since there is no path to VDD,
which forces repair high via the P transistor.  In neither date is
there any power dissipation by the circuit.  The outputs from the
circuit are used to compare the incoming address to the programmed
bad word or bit line.  In Fig. 3, out will have a logic value of
address if the fuse is not blown.  However, if the fuse is blown,
then the output will be equal to the...