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High Performance CMOS Receiver Circuit for Interfacing With TTL, ECL, NMOS Or CMOS Logic Circuits

IP.com Disclosure Number: IPCOM000100731D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 88K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

TTL, NMOS or CMOS logic circuits operated with single power supply produce a down level close to ground and an up level close to the power supply voltage. But an ECL logic circuit can be operated with two power supplies Vcc and VEE such that (Vcc-VEE) is constant. In present day designs, it is approximately 5.0 volts. An ECL logic circuit produces an output up level equal to (Vcc-VBE) and a down level (Vcc- 2VBE). Again, when Vcc 3.2V, ECL up level is 2.4V and down level 1.6V.

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High Performance CMOS Receiver Circuit for Interfacing With TTL, ECL, NMOS Or CMOS Logic Circuits

       TTL, NMOS or CMOS logic circuits operated with single
power supply produce a down level close to ground and an up level
close to the power supply voltage.  But an ECL logic circuit can be
operated with two power supplies Vcc and VEE such that (Vcc-VEE) is
constant.  In present day designs, it is approximately 5.0 volts.  An
ECL logic circuit produces an output up level equal to (Vcc-VBE) and
a down level (Vcc- 2VBE).  Again, when Vcc  3.2V, ECL up level is
2.4V and down level 1.6V.

      Presently designed CMOS receiver circuits can interface with
TTL, NMOS and CMOS circuits as the down levels provided by the
circuits in these technologies do not exceed the threshold voltage
(Vth) of the n-channel device in the CMOS technology.  But the down
level produced by the ECL off-chip driver will be close to twice the
Vth if one tries to maintain the up level within the CMOS or TTL
up-level specifications.

      An on-chip receiver circuit designed with standard CMOS devices
is disclosed which can receive signals from TTL, ECL, NMOS or CMOS
devices directly and which produce standard CMOS output levels.

      Referring to Fig. 1, the key feature of the circuit disclosed
is an n-channel device T3 (see circuit diagram) connected in series
with FET T2 .  The gate of T3 is tied to its drain at node
6.  Down level at the input of this receiver circuit will...