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New Circuit Configuration for NTL With Complementary Emitter-Follower Driver

IP.com Disclosure Number: IPCOM000100738D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Chuang, CTK: AUTHOR

Abstract

Disclosed is a new circuit configuration for NTL with complementary emitter-follower driver stage. Compared with the prior art (*), the present circuit configuration reduces the loading on the dotted collector node of the input transistors and improves both the pull-up and pull-down delays for a given power consumption.

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New Circuit Configuration for NTL With Complementary Emitter-Follower Driver

       Disclosed is a new circuit configuration for NTL with
complementary emitter-follower driver stage.  Compared with the prior
art (*), the present circuit configuration reduces the loading on the
dotted collector node of the input transistors and improves both the
pull-up and pull-down delays for a given power consumption.

      Fig. 1 shows the circuit configuration in the prior art (*)
where an additional emitter-follower transistor Q4 is used to drive
the base of the pull-down pnp transistor QD . The npn pull-up
transistor QU and the pnp pull-down transistor QD are configured in a
complementary emitter-follower configuration. In this scheme, Q4
represents a loading to the dotted collector node of the input
transistors, thus impacting both the pull-up and pull-down delays.
Furthermore, both the pull-up and pull-down delays are gated by the
load resistors RC1 and RC2.

      The disclosed circuit configuration (Fig. 2) utilizes a pnp
transistor Qpnp,4 to control the voltage at Node B.  The base of
Qpnp,4 is connected to the common emitter node of the input
transistors (Node A).  Thus, when any of the input rises to 'High',
the voltage at Node A follows immediately and turns off Qpnp,4 .
Node B is pulled down to VEE through R4, turning QD heavily on to
achieve fast pull-down of the output node.

      When the input goes down to 'Low', Node A is pulled down to VEE
through...