Browse Prior Art Database

Method for Making Vertical Coaxial Wiring

IP.com Disclosure Number: IPCOM000100741D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Wright, TM: AUTHOR

Abstract

By using sidewall spacer technology for both conductors and insulators, coaxial interconnection is made between selected levels of wiring. As an example, supply voltage VDD and ground wiring may be connected coaxially to upper wiring levels. This type of interconnection may be made at any of several stages of multilevel wiring formation.

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Method for Making Vertical Coaxial Wiring

       By using sidewall spacer technology for both conductors
and insulators, coaxial interconnection is made between selected
levels of wiring.  As an example, supply voltage VDD and ground
wiring may be connected coaxially to upper wiring levels.  This type
of interconnection may be made at any of several stages of multilevel
wiring formation.

      Referring to the figure, metal lines 2, 4, and 6 are deposited,
defined, and insulated from one another by conventional planarized
processing.  An opening of width W is then anisotropically etched
through all layers until metal line 4 is exposed.  Conductive
material is deposited conformally and anisotropically etched back
leaving conductive wall coating 8 and removing conductors 8 and 4 at
the bottom of the hole.  Insulating wall spacer 10 is then formed
similarly and metal layer 2 is exposed at the bottom of the hole
after etch-back is completed.  Conductor 12 is then deposited
conformally and may be defined to form a topmost level of wiring or
may be planarized as a stud to be interconnected to a next wiring
level.  Thus, if metal line 2 or 4 is a ground line and the other
is a VDD line, one potential is connected to line 6 and the other is
coaxially brought to the surface of the structure.

      Lower wiring levels may be interconnected to any other selected
upper wiring level or levels by variations in the sequence of the
foregoing process steps.