Browse Prior Art Database

Built-In Self-Test Architecture

IP.com Disclosure Number: IPCOM000100743D
Original Publication Date: 1990-May-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR [+3]

Abstract

An architecture for built-in selt-test (BIST) for AC and DC test of LSSD VLSI chips with embedded arrays is described. The BIST architecture allows seamless migration of chip test across all packaging levels--chip, module, card, system and field.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Built-In Self-Test Architecture

       An architecture for built-in selt-test (BIST) for AC and
DC test of LSSD VLSI chips with embedded arrays is described. The
BIST architecture allows seamless migration of chip test across all
packaging levels--chip, module, card, system and field.

      The novel ideas presented in this article are:
     -    use of a Common On-Chip Processor (COP) for
          self-test and system debug and diagnosis,
     -    use of an On-Card Sequencer (OCS) with on-chip
          nonvolatile arrays for the control of self-test
          and system initialization,
     -    use of a serial bus (COP bus) with a common
          protocol for both OCS to COP and Engineering
          Support Processor (ESP) to COP communications,
     -    inclusion of self-test hardware without modifying
          the LSSD scan structure such that LSSD diagnosis
          still applies,
     -    fast parallel on-chip array self-test, and
     -    fast parallel chip self-test at all packaging
          levels.

      The BIST architecture and its components are described. Then,
the operations made possible by this architecture are outlined.

      The figure depicts a card implementing the BIST architecture.
The following elements make up the architecture:
     -    LSSD VLSI chips with boundary scan SRLs and a
          dedicated COP,
     -    OCS, an off-the-shelf microcontroller with on-chip
          nonvolatile storage,
     -    Engineering Support Processor (ESP), a PC or RT PC
          workstation equipped with hard disk for permanent
          file storage, and
     -    a unique serial communications bus with a bus
          protocol common for COP, OCS and ESP.

      Note that only chips A, B and C are part of the BIST scheme,
since they contain a COP and are connected to the COP bus.  Chips D
and E do not have a COP; hence, they are not part of the BIST
architecture.

      The Engineering Support Processor ESP is a workstation capable
of running large programs from its permanent storage (hard disk).
The ESP is intended for engineering bring-up and debug of the system
and is not part of the system. During its operation, the ESP
overrides the OCS (by asserting the OCS override signal), thus
becoming the sole controller of the COP bus.

      The ESP can issue three classes of commands:  debug, system and
test.  Debug commands are used only during engineering bring-up and
require diagnostic programs to be executed and large data files to be
manipulated (for example, a dump of all system SRLs).  System
commands are part of the normal system set-up (for example, system
initialization or parity error handling).  Test commands control DC
chip-to-chip wiring test and stand-alone chip AC and DC self-test for
...