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Fast Sticky Bit Design for a 67-Bit Aligner in an IEEE 754 Floating-Point Coprocessor

IP.com Disclosure Number: IPCOM000100760D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Steimle, A: AUTHOR

Abstract

Disclosed is a logic circuit to produce the sticky bit of a 67-bit aligner as fast as the other bits. The sticky bit keeps trace of significant bits shifted out of the aligner. The assumption is that, in a fast coprocessor, the controls are latched.

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Fast Sticky Bit Design for a 67-Bit Aligner in an IEEE 754 Floating-Point Coprocessor

       Disclosed is a logic circuit to produce the sticky bit of
a 67-bit aligner as fast as the other bits. The sticky bit keeps
trace of significant bits shifted out of the aligner. The assumption
is that, in a fast coprocessor, the controls are latched.

      Circuit Description and Functionality The mantissa number is
written B0, B1, B2, B3.......B66, B0 being the most significant bit
and B66 being the sticky bit.

      The controls to shift right the bits from 0 to 7 are SHR0,
SHR1, SHR2, SHR3, SHR4, SHR5, SHR6 and SHR7.

      The controls to shift right the groups are multiples of eight:
SHR00, SHR08, SHR16, SHR24, SHR32, SHR40, SHR56, SHR64 and SHR64S (=
or > 64), SHR72S (= or > 72) just for the sticky bit.

      The preliminary assumption means the controls are available
before the data to be shifted. The "ORing" of the controls instead
the data bits is then the right solution to produce the sticky bit.

                            (Image Omitted)

A = SHR0 + SHR1 + SHR2 + SHR3 + SHR4 + SHR5 + SHR6
+ SHR7 = 1 because one of the controls is always active.
B = SHR1 + SHR2 + SHR3 + SHR4 + SHR5 + SHR6 + SHR7
=  SHR0 C = SHR2 + SHR3 + SHR4 + SHR5 + SHR6 + SHR7
=  (SHR0 + SHR1) D = SHR3 + SHR4 + SHR5 + SHR6 + SHR7
=  (SHR0 + SHR1 + SHR2)
E = SHR4 + SHR5 + SHR6 + SHR7 =  (SHR0 + SHR1 + SHR2
+ SHR3) F = SHR5 + SHR6 + SHR7
G = SHR6 + SHR...