Browse Prior Art Database

Direct Memory Access Transfer Control Technique

IP.com Disclosure Number: IPCOM000100765D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Krosschell, KD: AUTHOR [+2]

Abstract

Intermediate and large systems use intelligent I/O processors to perform data storage and retrieval. Moving this function out of the main system processor allows it to run other applications while the I/O processor is moving data to/from the physical devices. The system is structured with multiple I/O processors attached to a common bus with the main processor. Attached to the I/O processor(s) are the actual devices (DASD, tape, etc.).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Direct Memory Access Transfer Control Technique

       Intermediate and large systems use intelligent I/O
processors to perform data storage and retrieval.  Moving this
function out of the main system processor allows it to run other
applications while the I/O processor is moving data to/from the
physical devices.  The system is structured with multiple I/O
processors attached to a common bus with the main processor.
Attached to the I/O processor(s) are the actual devices (DASD, tape,
etc.).

      A DASD operation can be broken down into 5 steps.
1.   The system processor sends a message to the I/O processor
indicating it needs to have an I/O operation performed.
2.   The I/O processor performs a DMA transfer across the bus,
fetching a block of information describing the transfer to be
performed.
3.   The I/O processor DMAs the desired information across the bus
to/from the main processor.
4.   The I/O processor DMAs a block of status information to the main
processor.
5.   The I/O processor sends a message to the main processor
indicating that the operation is completed.

      Of the three DMAs, only the data transfer contains any
significant amount of data.  But all three DMAs invoke code layers
and the interrupt handler.  One code layer requests a DMA.  Another
code layer sets up the DMA control registers and issues the
operation.  An interrupt signals the completion of the DMA. Code then
tests the status registers for good completion and sends a message to
another code layer that the operation completed.  The layered code
structure allows the necessary error recovery actions to be performed
should an error occur.  A disadvantage is that the layering slows the
transfer while the code is passing and handling the control blocks.

      The control process can be improved by enhancing the I/O
processor to allow it to map all of the system's storage into its
memory map.  This new feature simplifies the control by allowing the
I/O processor to treat the main processor's memory as virtual
storage.  (In fact, the I/O processor can treat the memory of another
I/O processor as virtual storage also.)  The new hardware function
would include a cache to further improve the throughput of sequential
reads and writes.

      The I/O processor will reserve a 2-megabyte address space for
virtual addressing to the other cards on the bus. Any reads or writes
to this address space will cause hardware to DMA that data between
the I/O processor and the selected destination card.

      Hardware will have a destination card address register and a
destination RAM offset register.  The destination card address
register is a 5-bit register that contains the bus address of the
card to be treated as virtual storage.  The destination RAM offset
register is a 32-bit register that contains an offset into the
destination card's address space.  The hardware uses these values to
generate the current address for virtual ac...