Dynamic Workload Balancing
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Krosschell, KD: AUTHOR [+2]
Described is a way of improving system performance by preventing two IOPs from monopolizing the system bus which increases bus capacity by allowing seven or more high performance I/O processor cards to reside on the same system bus.
Dynamic Workload Balancing
a way of improving system performance by
preventing two IOPs from monopolizing the system bus which increases
bus capacity by allowing seven or more high performance I/O processor
cards to reside on the same system bus.
bus has a single bus arbiter, but the I/O processor
cards themselves determine which card is granted the bus.
Arbitration uses one request line, one acknowledge line, three
priority lines, and a daisy-chained poll line. Each I/O processor
card will drive request and some of the three poll lines when it
requests use of the bus. When the arbiter detects a request, it will
drive the acknowledge bus to all the I/O processor cards. The I/O
processor card closest to the arbiter will receive a poll line first.
It will take the bus cycle if it is requesting the bus and if the
three poll lines are equal to its priority value. Otherwise, the IOP
will pass the poll on to the next card. The next card, if the poll
was passed to it, will do likewise.
must be followed: 1) An I/O processor
pass the poll if the priority lines are at a value greater than its
priority, 2) an I/O processor card may not request the bus if it is
currently using the bus, and 3) arbitration is overlapped with bus
usage. Unfortunately, with these rules, two high performance cards
can completely monopolize the system bus.
a way to implement round-robin arbitration on the
SPD I/O bus. The I/O processor cards dynamically change their
priority based on workload. An I/O processor card resets priority to
zero after it is granted the bus. Then every Nth time another I/O
processor card is granted the bus. When this I/O processor card has
request active, it increments its priority. In the worst case, this
would allow "C" (4/7/10/...) cards to round-robin access the bus
instead of 2 with the current implementation. (N=0 C=2, N=1 C=4, N=2
C=7, C=3N+1 if N>0)
C = number of I/O processor cards
N = maximum value registers will increment to
X = number of bits in the register to support a count from 0 to
cards that rarely access the bus could hardcode
their priority to a high level. The I/O processor cards would be
changing their priority immediately after another I/O processor card
was granted the system bus.
Worst-case example for N=2 C=7. Cards always want the bus.
1 2 3 4 5 6 7
3 3 3 3 3 3 3 IOP 1 gets the bus & sets its
pri to zero 0 3 3 3 3 3 3 IOP 2 gets the bus
& sets its pri to zero
0 0 3 3 3 3 3 IOP 3 gets the bus & sets its
pri to zero ...