Browse Prior Art Database

RAM With Asynchronous Reset

IP.com Disclosure Number: IPCOM000100768D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Berger, RW: AUTHOR [+4]

Abstract

A static RAM macro has been designed with the unique capability of simultaneously resetting all bits to 0.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 58% of the total text.

RAM With Asynchronous Reset

       A static RAM macro has been designed with the unique
capability of simultaneously resetting all bits to 0.

      RAM initialization is a common procedure during power-on.  It
is also required at the beginning of a self-test routine where RAM
contents must be known.  RAM initialization is usually accomplished
by counting through all addresses and writing 0 to each location.
Depending on the size of the RAM, this can be a lengthy process since
the total time to complete the initialization equals (clock cycle
time) x (number of RAM words).

      Special data security requirements have made an asynchronous,
all-at-once zeroization function necessary.  A growable RAM CLU2
macro configured to 64 x 8 has been redesigned to perform this
operation.  The modifications can be applied to any configuration
within the limits of the growable RAM subsystem.

      All RAM cells can be reset to 0 within the time of a single
write cycle.  This is accomplished from a single input Z0 and will
override all other operations while that input is active.  Otherwise,
timing follows that described for the RAM macro in EDS Manual 4640.
Porosity and overall RAM dimensions are virtually unchanged.
Performance including the 'write all zeros' function falls within the
conservative worst-case values given for the normal CLU2 RAM macro.
The worst-case power dissipated during zeroization is approximately
230 mW for 10 nsec (2300 pJ total).  Power b...