Browse Prior Art Database

Process to Reduce Single Event Upset (SEU) Sensitivity

IP.com Disclosure Number: IPCOM000100777D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Haddad, NF: AUTHOR [+2]

Abstract

Charged particles, such as cosmic rays, deposit charge as they pass through semiconductor chips. If a circuit node is hit, the charge will deposit in the depletion region of the junction, as well as along a funnel created by the particle path. If the charge amount collected by the node is greater than the critical charge upset (QCNT) of a latch, the latch will change state, resulting in a logic error. Build ing devices on epitaxial wafers with low resistivity substrates alleviates some of the problem by limiting the funnel length to the epitaxial layer. Considerable funnel length can still occur if the particle hits the node at an oblique angle, as shown in Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 71% of the total text.

Process to Reduce Single Event Upset (SEU) Sensitivity

       Charged particles, such as cosmic rays, deposit charge as
they pass through semiconductor chips.  If a circuit node is hit, the
charge will deposit in the depletion region of the junction, as well
as along a funnel created by the particle path.  If the charge amount
collected by the node is greater than the critical charge upset
(QCNT) of a latch, the latch will change state, resulting in a logic
error.  Build ing devices on epitaxial wafers with low resistivity
substrates alleviates some of the problem by limiting the funnel
length to the epitaxial layer.  Considerable funnel length can still
occur if the particle hits the node at an oblique angle, as shown in
Fig. 1.

      This article describes a process to surround the device
junction with a highly doped region to limit the funnel length for
both normal and oblique bits.  The process sequence is compatible
with CMOS or NMOS technology.

      A p+ silicon wafer is used as a substrate.  A polysilicon
epitaxial layer 13 is deposited on the wafer by standard processing
in which an N-well 15 is formed by implant.  A pad oxide layer 17 and
a pad nitride layer 19,21 are deposited through standard chemical
vapor deposition (CVD) techniques.  Next, the pad nitride layer 19,21
is patterned by a first photoresist layer 23 and a reactive ion etch
(RIE) step down to the pad oxide 17.  A second photoresist layer 25
is then applied and patterned to p...