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Low Series Resistance Source by Spacer Methods

IP.com Disclosure Number: IPCOM000100779D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 97K

Publishing Venue

IBM

Related People

Polavarapu, M: AUTHOR [+2]

Abstract

To gain performance and density, MOS devices are reduced in size according to the Scaling Principle of Dennard. Not all parameters can be scaled, however. Simultaneous reduction of junction depth and gate oxide thickness, necessary to prevent short channel effects, will cause a heightened electric field at the drain electrode edge. A sufficiently high field in the drain region will accelerate electrons over the oxide-silicon channel barrier. If the electrons are trapped in the oxide, undesirable hot electron effects will result.

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Low Series Resistance Source by Spacer Methods

       To gain performance and density, MOS devices are reduced
in size according to the Scaling Principle of Dennard.  Not all
parameters can be scaled, however.  Simultaneous reduction of
junction depth and gate oxide thickness, necessary to prevent short
channel effects, will cause a heightened electric field at the drain
electrode edge.  A sufficiently high field in the drain region will
accelerate electrons over the oxide-silicon channel barrier.  If the
electrons are trapped in the oxide, undesirable hot electron effects
will result.

      Processing techniques to minimize hot electron effects are
available.  One in particular relies on the formation of lightly
doped drains (LDDs) to distribute drain voltage over a wider
distance, thus lowering the electric field.  Lightly doped drains
suffer from an increased resistance in series with the device
channel, and the device transconductance is accordingly reduced.

      Sources and drains are created at the same time in today's
process technology; thus, we create a lightly doped source at the
same time that we create a lightly doped drain.  Series resistance is
then increased at both the source and drain channel edges, while hot
electrons are a problem only at the drain edge.  What is needed,
obviously, is a low series resistance source region in conjunction
with a lightly doped drain.  This disclosure offers a method to
obtain that condition.

      In "spacer" technology, a vertical step is produced in
photoresist resident on a polysilicon layer.  The intent is to
pattern a polysilicon line - a gate - or a method that is controlled
not by lithographic constraints but by the thickness of a deposited
film.  The first step in this procedure results in the geometry in
Fig. 1.

      The next step is to deposit a conformal LPCVD film (usually
TEOS) on this structure.  It is possible to use a range of materials
to accomplish this.  A conformal deposition is one that coats all
exposed areas, horizontal or vertical, to the same depth.  After
deposition, the situation will be as shown...