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Multi-Port Roms Using the Complementary Sensing Scheme

IP.com Disclosure Number: IPCOM000100780D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Lai, FS: AUTHOR

Abstract

This article relates generally to ROM (Read-Only Memory) layout technique and more particularly to the multi-port ROM cell design. Cell area reduction can be achieved by placing the signals of port 1 and port 2 in a complementary scheme.

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Multi-Port Roms Using the Complementary Sensing Scheme

       This article relates generally to ROM (Read-Only Memory)
layout technique and more particularly to the multi-port ROM cell
design.  Cell area reduction can be achieved by placing the signals
of port 1 and port 2 in a complementary scheme.

      In Fig. 1, the ROM cell is a layout in the conventional way
with M1 as the word line and M2 as the bit line. Usually, a distance
between the ROX regions and four poly lines is required.

      By using the complementary scheme shown in Fig 2, the signals
from port 1 and port 2 are always complementary to each other.  These
signals can be corrected by placing one more inverter driver after
the port 2 sensing amplifiers.  This scheme can be applied to a
multiple- dual-port scheme.  A 20% area reduction is found on a
dual-port ROM design.