Browse Prior Art Database

Implementation of RS Flip-Flop in Bipolar Technology

IP.com Disclosure Number: IPCOM000100787D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

Toh, KY: AUTHOR

Abstract

Disclosed is a new implementation of the RS flip-flop in bipolar technology. The new circuit implementation requires less transistors, consumes less power, and can be operated at a higher speed than the conventional implementation.

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Implementation of RS Flip-Flop in Bipolar Technology

       Disclosed is a new implementation of the RS flip-flop in
bipolar technology.  The new circuit implementation requires less
transistors, consumes less power, and can be operated at a higher
speed than the conventional implementation.

      A circuit diagram of an RS flip-flop and its true table are
shown in Fig. 1.  Note that in the NOR circuit implementation, when
RS = 11, the outputs QQ = 00; this is not an allowed state.  This
is an inherent limitation of the RS flip-flop.  It is the user's
responsibil ity to prevent such a state to occur.  The conventional
bipolar circuit implementation of the RS flip-flop is shown in Fig.
2, using a standard ECL circuit.  The worst-case set/reset to output
valid time is two gate delays.  Note that such an implementation is
not a suitable for complementary differential switching circuit
family.

      The new implementation concept is suitable for ECL, DCS and CML
circuit families.  It consumes less power and uses less transistors.
The CML implementation is shown in Fig. 3, and the ECL and DCS
implementation is shown in Fig. 4.

      The operation of the circuit is explained with reference to
Fig.  3.  The set and reset is controlled by S and R inputs, active
high, respectively.  When both S and R are low, the previous output
states are retained through the latching action of Q3 and Q4.
Emitter resistors R2 ensure that S and R can over-write the out...