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Browse Prior Art Database

Dual Gate Oxide Process for Dual Power Supply Applications

IP.com Disclosure Number: IPCOM000100795D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

By adding an additional masking step, appropriate gate dielectric thicknesses are provided in devices which will operate with different power supply voltages on the same chip. This technique may be used as part of a metal oxide silicon (MOS), complementary MOS (CMOS), or bipolar CMOS (BICMOS) process. Thus, two devices to be operated at different voltage supply levels may be made on the same chip without usual yield, performance, or reliability penalties.

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Dual Gate Oxide Process for Dual Power Supply Applications

       By adding an additional masking step, appropriate gate
dielectric thicknesses are provided in devices which will operate
with different power supply voltages on the same chip.  This
technique may be used as part of a metal oxide silicon (MOS),
complementary MOS (CMOS), or bipolar CMOS (BICMOS) process.  Thus,
two devices to be operated at different voltage supply levels may be
made on the same chip without usual yield, performance, or
reliability penalties.

      Fig. 1 is a cross section showing typical regions A, B, and C
representing low voltage device areas, NPN base regions, and high
voltage (thick gate dielectric) device regions, respectively.
Conventional device processing is used until gate oxide 10 having
thickness appropriate for low voltage MOS devices is grown on exposed
silicon 12 in regions A, B, and C.  Thin polysilicon layer 14 is
deposited and covered with SiO2 (oxide) 16 and Si3N4 (nitride) 18.
Region A is then protected by photoresist and layers 18, 16, and 14
are etched off regions B and C to result in the cross section shown.

      Referring to Fig. 2, thick gate oxide 20, for higher voltage
MOS devices, is grown in both regions B and C. Polysilicon 22, oxide
24, and nitride 26 are then blanket deposited.  An additional masking
step is used to protect region C while layers 26, 24, and 22 are
etched off regions A and B, leaving the condition shown in Fig. 2.
Part of oxid...