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Browse Prior Art Database

High-Performance Test System

IP.com Disclosure Number: IPCOM000100798D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Klink, E: AUTHOR [+4]

Abstract

Disclosed is a test system for ULSI (ultra-large scale integration) logic and memory chips which affords extremely low inductive connections at low force and by which the various chips on a wafer can be simultaneously tested. As a result, there are no performance limitations in testing and in the number of simultaneously switching internal circuits and off-chip drivers and their speeds.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

High-Performance Test System

       Disclosed is a test system for ULSI (ultra-large scale
integration) logic and memory chips which affords extremely low
inductive connections at low force and by which the various chips on
a wafer can be simultaneously tested.  As a result, there are no
performance limitations in testing and in the number of
simultaneously switching internal circuits and off-chip drivers and
their speeds.

      The basic idea is to use a silicon carrier, as is schematically
represented in the above sectional view, which, by metallizations M1
and M2, is brought into contact with the wafer to be tested.  These
two silicon parts are connected by copper dendrite/PbSn contacts.  On
the silicon carrier side, the dendrite is positioned on and fixed to
pads, whereas on the wafer, PbSn-C4 balls are placed in the usual
chip technology on the pad of wafer metallizations M1'to M3'.

      Because of the extremely flat surface of the two silicon parts
(< 50 mm), all chip site positions can be contacted in parallel and,
compared with standard needle contacts, only a small amount of force
is required.  From the back side of the silicon carrier, an adequate
fixture provides the necessary low-pressure force.

      The very close contact formed with the C4 dendrite connection
ensures an extremely low inductive path (approximate distance from
silicon carrier to wafer 100 mm).

      The usual inductance of a single needle contact is in the range
of...