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Browse Prior Art Database

Diagnostic Address Compare for Unauthorized Access to Shared Memory

IP.com Disclosure Number: IPCOM000100801D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 158K

Publishing Venue

IBM

Related People

Gatson, MS: AUTHOR [+3]

Abstract

This article describes a technique that allows detection of unauthorized accesses or updates to memory that is being shared between multiple masters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 38% of the total text.

Diagnostic Address Compare for Unauthorized Access to Shared Memory

       This article describes a technique that allows detection
of unauthorized accesses or updates to memory that is being shared
between multiple masters.

      An adapter memory can be read and written from multiple sources
as follows: -   from the direct memory access (DMA) channels to the
communication lines, -   from the DMA channels to a Micro Channel*, -
from direct access by the Micro Channel, or -   from an Intel 80186
processor.

      Without elaborate external test equipment, it is very difficult
to locate the source of unauthorized changes to data in this shared
memory.

      The technique disclosed herein implements the following four
registers to allow the detection of the unauthorized memory accesses.
1.   Memory base address.  This register is a 21-bit register to
allow a base address within any address of the 2-megabyte memory
address space.  The contents of this register select the base of the
memory to be monitored.  It also is used to contain the actual
address of a memory access when an address match occurs.  Other sizes
of this register can be implemented to allow more or less memory to
be monitored.
2.   Memory range value.  This register is implemented as a 16-bit
register to allow from 1 to 64K bytes of address to be monitored.
Other implementations of this register can allow for larger or
smaller amounts of memory addresses to be monitored.  In one
implementation, the bits that are set to a 1 determine which address
bits are treated as "don't care" address lines for the monitoring.
This causes the range and boundary of the memory area to be monitored
to be set. The usage of this register to select the memory boundary
allows for a simpler implementation than if any range on any memory
address were allowed.
3.   Control register.  This register is implemented as a 6-bit
register with the following options being assigned to individual
bits:
 -   Monitor all accesses or only write accesses,
 -   Block the memory from being altered on write accesses or allow
the write to update the memory,
 -   Monitor 80186 accesses, which includes the 80186 DMA access,
-   Monitor Micro Channel memory slave accesses,
-   Monitor communication DMA channel accesses, or
-   Monitor bus master DMA channel accesses.
      All combinations of bits turned on in this register are
      valid and the selected monitoring will be performed on
      the address area selected.
4.   Status Register.  This 13-bit register is a combination
      of multiple pieces of information depending on which
      source was detected accessing the memory being
      monitored.  It is set to provide information when an
      unauthorized access is detected.  The information
      provided is:
 -   Three bits to indicate the source of the access:
      -    80186 access
      -   ...