Browse Prior Art Database

Zip Module Package With Two Memory Chips

IP.com Disclosure Number: IPCOM000100804D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Hinrichsmeyer, K: AUTHOR [+4]

Abstract

Presently, memory chips are vertically mounted for maximum density by ZIPs or SIPs (zigzag or single inline packages). A ZIP contains only one memory chip, whereas a SIP module has a wired substrate to interconnect several memory chips or SOJs (small outline j-lead packages).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Zip Module Package With Two Memory Chips

       Presently, memory chips are vertically mounted for
maximum density by ZIPs or SIPs (zigzag or single inline packages). A
ZIP contains only one memory chip, whereas a SIP module has a wired
substrate to interconnect several memory chips or SOJs (small outline
j-lead packages).

      Proposed are slim memory carriers with cavities and wiring
slots, as described in German patent application P 39 11 711.1.  Two
of these carriers are back-to-back assembled on an intermediate layer
of discrete parallel wires/leads. The leads are contained in a frame,
representing a plane.

      Each lead is shaped such that it contains two special
extensions which can be bent in opposite directions, providing
appropriate connections for two chip carriers on either side of the
wire plane.  The lead may also be bent for fixing and connecting the
illustrated chip, thus providing only one extension.

      An extended section of the lead is used as an I/O pin, which
may also be shaped, after assembly of the carriers.

      All leads are preliminarily fixed to the lead frame by special
extensions which are cut off during assembly.  The lead frame itself
is cut out of an about 0.2 mm thick metal laminate by punching or
etching.  The lead extensions are soldered or brazed to the carrier
I/O pads.