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High Stud-To-Line Contact Area in Damascene Metal Processing

IP.com Disclosure Number: IPCOM000100814D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Cronin, JE: AUTHOR [+3]

Abstract

When line width is equal to stud width, line-to-stud contact area is assured to be no less than the area of contact under perfect alignment conditions throughout the range of misalignment tolerance by adding vertical wall contact area under misalignment conditions. Thus, line- to-stud electrical contact resistance is never higher than resistance when alignment is perfect and least when slight misalignment occurs. Since slight misalignment has the highest probability of occurrence, low contact resistance has the highest probability of occurrence. Two process methods are described to create added sidewall contact area when misalignment occurs.

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High Stud-To-Line Contact Area in Damascene Metal Processing

       When line width is equal to stud width, line-to-stud
contact area is assured to be no less than the area of contact under
perfect alignment conditions throughout the range of misalignment
tolerance by adding vertical wall contact area under misalignment
conditions.  Thus, line- to-stud electrical contact resistance is
never higher than resistance when alignment is perfect and least when
slight misalignment occurs.  Since slight misalignment has the
highest probability of occurrence, low contact resistance has the
highest probability of occurrence.  Two process methods are described
to create added sidewall contact area when misalignment occurs.

      A first process is described by referring to Fig. 1. Insulator
10 is applied over substrate 12, thin etch stop layer 14 is
deposited, insulator 16 is applied, and a second etch stop 18 is
deposited.  Photo processing is used to define stud regions, and
layers 18, 16, 14, and 10 are successively etched away from the stud
regions.  This, and all subsequent etching is shown to be by an
anisotropic process.  Conductor 20 is conformally deposited and
planarized to expose etch stop 18.  Insulator 22 is then deposited
and covered by etch stop 24.  A photo mask is used to define a line,
and the exposed regions of layers 24, 22, 18, and 16 are removed by
successive etching steps to form a cavity for a conductive line.
Conductor 26 is conformally deposi...