Browse Prior Art Database

Silicon-On-Silicon - The Integral Decal

IP.com Disclosure Number: IPCOM000100820D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Jacobs, SL: AUTHOR [+4]

Abstract

A high performance integral decal technology for application to silicon substrate packaging designs is described in this article. Low dielectric polyimide and lithography techniques are uniquely combined, in the disclosed procedures, to obtain significant improvements in circuit utilization and I/O connection reliability over that offered by current technology.

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Silicon-On-Silicon - The Integral Decal

       A high performance integral decal technology for
application to silicon substrate packaging designs is described in
this article.  Low dielectric polyimide and lithography techniques
are uniquely combined, in the disclosed procedures, to obtain
significant improvements in circuit utilization and I/O connection
reliability over that offered by current technology.

      The density of inner lead terminals (pad connections) in
current silicon substrate packaging technology (TAB) is limited by
the resolution attainable for the alignment of mechanical bonding
techniques; e.g., TAB technology can provide only a 120-micron pitch
for inner lead bonding pads. The high performance integral decal
technology here introduced can, on the other hand, easily achieve a
50-micron smaller pitch, thereby offering a 5 to 6 times improvement
in circuit utilization.  Basic differences in approach between the
two technologies are shown in Figs. 1A and 1B.

      In Fig. 1A, the TAB technology is shown to involve mechanically
bonding the tab pads 1 to the chip I/O's 2. This makes necessary the
use of large solder pads 3 and 4 on both the chip 5 and substrate
6, requiring that the inner lead I/O pads be 120 microns or more in
feature size.

      Fig. 1B illustrates the integral decal technology, in which
inner lead connection feature size is dependent only on the present
limits of lithography, i.e., equal to or less than 50 microns.  This
is due to the fact that the decal is integrated (completely bonded)
to the chip.  The integration of decal and chip also contribute to a
more reliable I/O connection since thermal mismatch stresses are
taken up by the total available chip surface rather than just by the
area of interconnection.

      Figs. 2-8 illustrate steps in the integral decal manufacturing
process.

     ...