Browse Prior Art Database

Silicon-On-Silicon CMOS Optimized Package

IP.com Disclosure Number: IPCOM000100822D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Jacobs, SL: AUTHOR [+4]

Abstract

This article concerns a novel packaging application for the CMOS technology in which CMOS chips are assembled on a silicon substrate. A plurality of these populated silicon substrates are then mounted on a board or card to achieve an extremely high packaging density to form a module carrier.

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Silicon-On-Silicon CMOS Optimized Package

       This article concerns a novel packaging application for
the CMOS technology in which CMOS chips are assembled on a silicon
substrate.  A plurality of these populated silicon substrates are
then mounted on a board or card to achieve an extremely high
packaging density to form a module carrier.

      CMOS technology requires singular features in its packaging
because of its unique characteristics:
   1.   CMOS chips are very dense, typically, 50,000 circuits per
chip.
      2.   CMOS chips usually require only two voltage supply levels,
namely, +5.0 and 0 volts.  Signal swings are therefore large which
make them less sensitive to noise.
      3.   CMOS circuits have low power dissipation, perhaps an order
of magnitude less than their bipolar equivalent; consequently, CMOS
package cooling is relatively simple.

      Fig. 1 is a schematic plan view of the silicon-on-silicon
substrate 1 containing a 3 x 3 matrix of CMOS chips 2.  Also shown
are the inter-module wiring 4 and 5, comprising signal and power
lines.

      Fig. 2 shows a diagramatic view of a module carrier 3, usually
made of metal clad material and supporting a 2 x 3 matrix of
populated silicon-on-silicon substrates 1.  A plurality of E.C. pads
6 are shown at the periphery of the silicon-on-silicon substrate 1.

      A plurality of silicon-on-silicon substrates 1 (each preferably
employing a matrix of 3 x 3 CMOS chips 2 as shown in Fig. 1)
are used in the disclosed silicon-on-sil...