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Means for Limiting the Cache-Reload Transient Caused by Interrupt Programs

IP.com Disclosure Number: IPCOM000100831D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 147K

Publishing Venue

IBM

Related People

Stone, H: AUTHOR [+2]

Abstract

The technique described here can eliminate some of the performance penalty caused by the cache-reload transient of an interrupt program.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Means for Limiting the Cache-Reload Transient Caused by Interrupt Programs

       The technique described here can eliminate some of the
performance penalty caused by the cache-reload transient of an
interrupt program.

      Thiebaut and Stone (1) showed that an interrupting program
displaces an interrupted program from a cache memory, and thus causes
future performance degradation when the interrupted program regains
control of the processor and has to reload itself into the cache.
Stone, Wolf, and Turek (2) showed that a least-recently-used (LRU)
replacement strategy in a cache memory causes more misses than a
strategy that limits the growth in cache memory allocation of a
program as it reaches the end of its quantum.  The scheme discussed
here is a means for limiting the cache allocation of an interrupt
program in order to reduce cache misses by the interrupted program.
The objective is to compute a cache limit for an interrupt program,
and this, in turn, will limit the misses due to the reload transient
of the program to which it returns.  To achieve the objective, we
exploit a model of cache behavior, and determine the optimum cache
allocation according to the parameters of that model.  The optimum
allocation turns out to be relatively insensitive to the parameter
values.

      The Cache Model For this discussion we assume that interrupt
programs have the following characteristics:
1.   When the interrupt program is invoked, all of its active lines
fit concurrently in cache.
2.   When the interrupt program completes execution, it returns to
the interrupted program,
3.   All cache lines of the interrupted program that have been
displaced by the interrupted program are reloaded into the cache and
cause misses that would not have been present if the interrupt had
not occurred.
4.   The interrupted program runs to completion without itself being
interrupted.
Using the model of Thiebaut (3), we assume that unique lines accessed
by the interrupt program as a function of time obey the equation

                            (Image Omitted)

   u(t) =  AtB                                        (1) and the
miss ratio for the interrupt program operating in a cache of size C
lines is given by
   MR(C) = BA1/BC1-1/B                                (2)

      Limiting the Cache-Reload Transient Suppose that the interrupt
program runs for time T.  We propose to permit the interrupt program
to obtain additional cache memory when it initiates execution up
until some critical cache size or critical execution time is reached.
After that point, the interrupt program uses a replacement rule that
displaces its old lines when new ones are brought to the cache, which
prevents the cache allocation of the interrupt program from growing.
(In practical implementations, the cache is set associative rather
than fully associative, and this...