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Hybrid Switch for a Highly Parallel Message Passing System

IP.com Disclosure Number: IPCOM000100836D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 4 page(s) / 124K

Publishing Venue

IBM

Related People

Genco, SM: AUTHOR [+5]

Abstract

There is traditionally a trade-off between cost and performance in processor interconnection networks for message-passing systems. This article describes a Hybrid interconnection network that combines two switching architectures for an optimal cost/performance trade-off.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hybrid Switch for a Highly Parallel Message Passing System

       There is traditionally a trade-off between cost and
performance in processor interconnection networks for message-passing
systems.  This article describes a Hybrid interconnection network
that combines two switching architectures for an optimal
cost/performance trade-off.

      The following are definitions used for the purposes of this
article:
-    A processing node is one or more processors connected to a
shared memory.  An example might be two processors (CPs) with 128 MB
of shared memory.
-    An I/O node is a set of hardware to buffer and processes DASD or
other I/O device data.
-    A very large system consists of many processing and I/O nodes in
a balanced system connected together via a switching network.  The
switching network provides the means to pass data and control
information from one node to another.
-    The switch bandwidth is the total rate that 'packets' or
'messages' of data can be passed simultaneously through the switching
network.

      Crossbar Switching Networks A highly parallel message passing
system may contain hundreds or even thousands of processing nodes and
I/O nodes.  The ideal switching network for such a system is a
central switch that connects any node to any other node and can
process all node requests concurrently with little delay (switch
latency).

      A near ideal implementation of this type of network is an input
queued nonblocking crossbar switch, as illustrated in Fig. 1.  This
is a single level switch in that any request propagates from the
input of the switch to an output through only one arbitration cycle.
If all queues are empty, the latency for this crossbar switch will be
three to four machine cycles.  The crossbar switch bandwidth is the
sum of the individual node bandwidths.

      Two factors limit the size of practical crossbar switch
designs.  First, as the number of nodes N grows, with an assumed
constant machine cycle, it becomes prohibitively expensive to design
circuitry that can arbitrate one of the inputs in one machine cycle.
For a competitive cycle time and known technologies, the maximum
limit is in the range of 25 to 50 node connections.  Second, for wide
node connections (90 signals or more), the chip, card, and frame I/O
limit the practical size of the crossbar switch, dictated by the
available signal I/O in the technology under consideration.  For a
very large system of several hundred nodes...