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Improved Wiring Methodology Suitable for Automated Wiring Programs That Decreases Interconnected Lengths

IP.com Disclosure Number: IPCOM000100840D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 70K

Publishing Venue

IBM

Related People

Rizzolo, RF: AUTHOR

Abstract

Present interconnect wiring between chips on a common carrier (module, board, or card) is done using multiple planes of X-Y wiring, as shown in Fig. 1. This type of wiring is well suited to automated wiring programs where one carrier must support a number of different chip configurations.

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Improved Wiring Methodology Suitable for Automated Wiring Programs That Decreases Interconnected Lengths

       Present interconnect wiring between chips on a common
carrier (module, board, or card) is done using multiple planes of X-Y
wiring, as shown in Fig. 1.  This type of wiring is well suited to
automated wiring programs where one carrier must support a number of
different chip configurations.

      The vertical connections between different X and Y wiring
planes are called vias.  These vias are presently loaded on a square
grid.  One or more wires may pass between these via grid locations.

      The problem with this wiring methodology is that the
interconnect distance between the chips is significantly greater than
the straight line distance because the wiring is forced into X or Y
channels (see Fig. 2).

      The following wiring scheme decreases the interconnect length
between chips without decreasing the via-line spacing and only
decreasing the via density by 15%.  The basic features are shown in
Fig.  3 and described as follows:
(1)  a via pattern based on hexagonal close packing (staggered grid);
(2)  horizontal wiring is done using multiple plane triplets U, V, W;
(3)  wiring on each plane is at an angle of 60 degrees with respect
to every other plane.

      In order to determine the amount that the interconnections will
be decreased, calculations have been shown in Figs. 4 and 5.  The
resulting interconnection length decrease...