Browse Prior Art Database

Dynamic Logic Protection Circuit

IP.com Disclosure Number: IPCOM000100847D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 84K

Publishing Venue

IBM

Related People

Zalph, WN: AUTHOR

Abstract

A dynamic logic protection circuit is described which protects integrated circuits (ICs) from being damaged during power-up or power-down or in the event a clock signal is lost. The circuit disclosed herein ensures that a clock signal is present before power is applied to dynamic integrated logic circuitry and that the circuit removes power to an IC chip if a clock signal should fail, thereby protecting the internal elements of the IC.

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This is the abbreviated version, containing approximately 52% of the total text.

Dynamic Logic Protection Circuit

       A dynamic logic protection circuit is described which
protects integrated circuits (ICs) from being damaged during power-up
or power-down or in the event a clock signal is lost.  The circuit
disclosed herein ensures that a clock signal is present before power
is applied to dynamic integrated logic circuitry and that the circuit
removes power to an IC chip if a clock signal should fail, thereby
protecting the internal elements of the IC.

      Typically, dynamic logic circuits use a clock signal to
alternatively switch internal logic between precharge and validation
cycles, as shown in Fig. 1.  If the clock signal is in an
indeterminate state, the precharge and validation devices may be ON
simultaneously, causing a large current flow.  In this case, the
device will be stressed to the extent that the mean time between
failure will be reduced. In addition, certain IC chips cannot
tolerate power to the circuits before a clock signal is applied.
During a power-down operation, the clock signal may not be present to
the IC, thereby causing damage to the chip.  The concept described
herein implements a circuit to prevent damage to IC chips.

      The protection circuit of this disclosure, as shown in Fig. 2,
is designed to effectively isolate an IC chip from its decoupling
network, thereby allowing the IC input voltage to go to zero as
quickly as possible.  If the clock fails, the circuit will remove
power to the IC.  At power-on time, +5V comes up, enabling the clock
signal to be applied at node 10.  At the same time, node 11 will be
at +3V, due to power field-effect transistor (FET) 12, which has a
VgsSAT / 2V. Power FET 12 will turn ON to provide a ground level at
node 13,...