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Distributed Control Facility for Interrupt And Critical Region

IP.com Disclosure Number: IPCOM000100848D
Original Publication Date: 1990-Jun-01
Included in the Prior Art Database: 2005-Mar-16
Document File: 3 page(s) / 90K

Publishing Venue

IBM

Related People

Fukuda, M: AUTHOR [+5]

Abstract

Disclosed is a facility for controlling interrupts and critical regions efficiently in the multiprocessor system. The basic idea is to use the dependency table for deciding whether the system should start or suspend the services of the interrupts and the critical regions. The facility is implemented in a controller explained below.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Distributed Control Facility for Interrupt And Critical Region

       Disclosed is a facility for controlling interrupts and
critical regions efficiently in the multiprocessor system. The basic
idea is to use the dependency table for deciding whether the system
should start or suspend the services of the interrupts and the
critical regions.  The facility is implemented in a controller
explained below.

      Fig. 1 shows the hardware configuration for implementing the
facility.  Each processor in the system has a controller.  The
controller primarily consists of an interrupt mask register (IMR), a
dependency table, and a current service register (CSR).  Every
controller examines the external interrupts.  The IMR is used for
grouping interruptible processors for the same interrupt level.  The
dependency table shows the dependency between the shared data and
interrupts. The CSR records the interrupts and the critical regions
in service in the entire system.

      The sequence for controlling interrupts is as follows. The IMR
tests an incoming interrupt to check whether the controller can
receive it or not. Secondly, the dependency table examines the
interrupt through the IMR to see whether the processor should accept
or suspend it. This sequence may be done by more than two different
interrupt controllers in the same interruptible group.   But the
controllers participate in the bus access arbitration to determine a
single interruptible processor.  The controller which wins this
arbitration updates its CSR, and notifies the interrupt to its
processor.

      Fig. 2 shows the control mechanism imposed by the dep...